1. Field of the Invention
The present invention relates to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an isolation structure and a fabrication method thereof. More particularly, the present invention relates a MOSFET with an isolation structure formed through a low voltage complementary metal oxide semiconductor (LVCMOS) manufacturing process.
2. Description of Related Art
The integrated control circuit and driver transistor techniques have become the development trends of current power ICs. Therefore, it is a better solution for monolithic IC integration to use a standard manufacturing process to fabricate transistor devices. However, transistors fabricated by using the current standard manufacturing process are non-isolation structures, and a non-isolated transistor current could flow around the substrate. This may generate noise interference in the control circuit. Moreover, this transistor current can generate a ground bounce to disturb the control signals of the control circuit. Therefore, transistors of non-isolation structures are not suitable for the integration technique.
Referring to FIGS. 1 and 2, schematic circuit diagrams of an N-type and a P-type MOSFET are shown. As shown in the figures, the N-type MOSFET (NMOS) 10 includes a drain 20, a source 30, and a gate 40. The P-type MOSFET (PMOS) 50 includes a drain 60, a source 70, and a gate 80.
Referring to FIG. 3, a structural cross-sectional view of a conventional MOSFET is shown. As shown in the figure, an N-type MOSFET 10 and a P-type MOSFET 50 include a P-type substrate 100, an N+ buried layer 860 and a P+ buried layer 880 formed in the P-type substrate 100, an N-type epitaxial layer 660 and an N-type epitaxial layer 680 respectively formed on the N+ buried layer 860 and the P+ buried layer 880.
Furthermore, the conventional transistor isolation structure uses the N-type epitaxial layer 660 to surround a first drain region 230 and a first P-type region 220 of the N-type FET 10, and uses the N-type epitaxial layer 680 to surround a second source region 440, a second contact region 450, and a second P-type region 420 of the P-type FET 50. Meanwhile, a plurality of separated P+ regions 500 having P+ ions is formed between the N-type epitaxial layers 660 and 680, so as to provide isolation between the MOSFETs. However, the isolation structures formed by the above conventional method have drawbacks of a complicated manufacturing process and a high fabrication cost.